The present invention relates generally to an electrically erasable programmable non-volatile semiconductor memory device, in which a memory, comprising an electricity-charging floating gate electrode and a control gate electrode stacked thereon, is used as a memory cell, and more particularly to a NAND EEPROM (electrically erasable programmable ROM) in which a plurality of memory cells are connected in series.
FIG. 1A is a plan view showing one memory cell column of a conventional NAND EEPROM, and FIG. 1B is a diagram showing an equivalent circuit of the memory cell column shown in FIG. 1. FIG. 2 is a cross-sectional view of the memory cell column shown in FIG. 1A, taken along the line II--II. FIG. 3 is a cross-sectional view of the memory cell column shown in FIG. 1A, taken along the line III--III.
The memory cell column is formed in a double-diffusion type p-well 11 formed in a p-type semiconductor substrate. Each of the memory cells of the column has an electricity-charging floating gate electrode 14 and a control gate electrode 16. In the following description, the memory cell may be called simply a cell. As shown in the drawings, the memory cell column is constituted by a plurality of stacked-type memory cells M1 to M8 connected in series and controlled by control gates CG1 to CG8. Selection transistors S1 and S2 are respectively provided on both ends of the serially-connected memory cell column, i.e., on both a drain D side and a source S side. Selection gates SG1 and SG2 of the selection transistors S1 and S2 control the connection or disconnection between a bit line 18 of the memory cell column on one hand and a common source line on the other. In FIG. 3, a reference numeral 17 denotes an interlayer insulating film. In FIG. 2, elements 14.sub.9 and 14.sub.10 are electrically connected to each other, and elements 16.sub.9 and 16.sub.10 are electrically connected to each other in a region (not shown) to form the selection gate SG1 and SG2, respectively.
FIG. 4 shows voltages applied to the respective portions in erasing, writing and reading operations in the memory cell described above. The operations and problems thereof will be described below.